Design Rule Aware VLSI Physical Design Framework for Enhancing Chip Performance, Reliability and Manufacturability
Keywords:
VLSI Physical Design, Design Rule Checking, Design for Manufacturability, Reliability Optimization, Placement and Routing, Semiconductor Manufacturing, Physical Verification, Electronic Design AutomationAbstract
The continuous scaling of semiconductor technologies has significantly increased the complexity of Very Large-Scale Integration (VLSI) physical design. Modern integrated circuits require strict adherence to design rules while simultaneously achieving high performance, reliability, and manufacturability. Design rule violations can negatively impact yield, increase production costs, and reduce device lifetime. This paper presents a review of design rule-aware VLSI physical design methodologies that integrate design rule checking, placement optimization, routing constraints, and manufacturability considerations throughout the design flow. The study examines developments in physical design automation, reliability-aware optimization, and design-for-manufacturability (DFM) techniques. The findings indicate that incorporating design-rule awareness during placement and routing stages improves timing performance, reduces manufacturing defects, enhances yield, and increases overall chip reliability. The review highlights emerging trends in machine learning-assisted physical design and advanced design rule optimization for future semiconductor technologies
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Copyright (c) 2026 Ranjith Murugesan (Author)
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
